Digital and analogue Electronic

Paper details:

Analogue:
A remote motor speed sensor provides a current signal in the range of -2.5 to 2.5 mA. Design a circuit to
convert this signal into a voltage signal in the range from 2 to 3 V. After the conversion, a low pass filter is
used to suppress any noise AC signals with frequency higher than 50 Hz.
Digital:
An 8-bit analogue-to-digital converter will be given and should be used to convert the output of the above
analogue circuit into an 8-bit digital signal. The 8-bit signal should go through two 4-to-7 decoders so that
the value of the 8-bit digital signal is displayed as two hexadecimal values on two seven-segment display
devices to indicate the safe running speed of the motor in range 0-255 (i.e. 00hex to FFhex).
Part 1: Design a current amplification and filtering circuit [40 marks]
Use an AC current source with a very low frequency of 0.01 Hz to emulate the slowly changed current
output signal from the remote motor speed sensor. Design the current amplification circuit using
appropriate op-amp circuits so that you can achieve the required output voltage (2 to 3 V). Demonstrate
the gain, Bandwidth, Rin of your op-amp circuits by both calculation and simulation.
Design the low-pass filter. Demonstrate the bandwidth of the filter by both calculation and simulation.
Combine the op-amp circuit and the filter. Demonstrate the gain, Bandwidth, phase shift, Rin of your
combined circuit by both calculation and simulation.
Marks allocation:
a) Current sampling/amplification circuit: [15 marks]
b) Low-pass filter circuit: [15 marks]
c) Combined circuit: [10 marks]
Liverpool John Moores University Coursework 4304ELE Digital and Analogue Electronics
W. Zhang / O. Dordevic 2017/2018 Page 4 of 9
Part 2: Design an 8-bit counter and a 4-to-7 decoder for the Seven-Segment display [40 marks]
The output voltage signal from the analogue circuit should then be converted into an 8-bit digital signal,
which represents the levels of the motor speed. You can choose the generic 8-bit ADC device from the
Proteus library => Modelling Primitives => ADC_8 for this task. Following is an example connection of the
ADC convertor that you can refer to when you design your circuit.
2.1) 8-bit counter design
Design an 8-bit synchronous counter by using D-type flip-flops. The counter should be driven by a CLK signal
running at 256k Hz. You should show how the counter is designed, and simulate the circuit.
Marks allocation: [15 marks]
The MSB output of the counter should be used to connect to the clock terminal of ADC_8 converter. The
value of the output of the ADC_8 converter should be displayed in two 7-segment display units. The MSB
four bits are displayed in one and the LSB four bits in another 7-segment display. In order to achieve this,
you should design the 4-to-7 decoder for the 7-segment display, as detailed below.
2.2) 4-to-7 decoder design
A 7-segment display decoder is commonly used to display a particular number representation using a
display composed of seven LED segments. The diagram below represents a 7-segment display decoder
which converts a 4-bit binary number into a collection of symbols to be displayed:
7-segment decoder a
b
c
d
e
f
g
a b
c d e
f
g x3
x2
x1
x0
Liverpool John Moores University Coursework 4304ELE Digital and Analogue Electronics
W. Zhang / O. Dordevic 2017/2018 Page 5 of 9
Your 7-segment decoder should accept a 4-bit binary numbers [x3, x2, x1, x0], which represent integer
numbers 0 – 9 and letter A, B, C, D, E, F (i.e. which represent hexadecimal value in range 0hex to Fhex). A 7-
segment display with common anode should be used, i.e. the decoder should output “0” to switch on the
corresponding LED segment (a-g) of a 7-segment display shown above. The symbols used should be:
Complete the truth table for the 4-to-7 decoder: Use Karnaugh map to simplify the logic expressions for the
4-to-7 decoder. You can use all available gates (some of them are listed below). Simulate your decoder
circuit and demonstrate that the circuit is working properly.
Marks allocation: [15 marks]
2.3) Combined digital circuit
Connect the outputs of the 8-bit ADC to two 4-to-7 decoders which drive two seven-segment display units,
respectively. Simulate the circuit and demonstrate that entire circuit works properly.
Marks allocation: [10 marks]
You could use the logic components in the Proteus library TTL/74LS:
D Flip-Flop: 74LS74N
2-input AND gate: 74LS08N Inverter: 74LS04N
2-input NAND gate: 74LS00N 3-input NAND gate: 74LS10N
4-input NAND gate: 74LS20N XOR gate: 74LS86N
NOTE
You may also use the counter and 4-to-7 decoder given in the Proteus library, but you will only receive
maximum 10 marks for task 2.1) and maximum 10 marks for task 2.2) if you do so.
What you should hand in
Once you have completed the designs, prepare for the submission process. You are required to submit a lab
report (less than 10 pages) including:
• The detailed description and calculation of your design.
• Circuit schematic with clear comments.
• The simulation results, waveforms.
• Discussions of your design problems, methods of improvement and conclusions.
Refer to the report marking scheme for the detailed requirements.
If your circuit is not completely functional by the due date, you should turn in what you have to receive
partial credit. Late submission will be penalised. Refer to the assignment marking scheme for details