MIPS Computer Architecture

MIPS Computer Architecture
Clock Cycle Time. Given these timings of individual stages of the datapath:

IF: 250ps

ID: 200ps

EX: 150ps

MEM: 160ps

WB: 140ps

(a) What is the clock cycle time of a multi cycle processor? Briefly explain why (1-2 sentences).

(b) What is the clock cycle time of a single cycle processor? Briefly explain why

(c) How long does a lw instruction take to execute in a multi cycle processor using these timings?

(d) How long does a lw instruction take to execute in a single cycle processor using these timings?